PRECISE Seminar: Predictable Integration of Safety-Critical Software on COTS-based Embedded Systems

Building safety-critical real-time systems out of inexpensive, non-realtime, COTS components is challenging. Although COTS components generally offer high performance, they can occasionally incur significant timing delays. To prevent this, we propose two approaches: 1) a new "clean slate" real-time, memory-centric scheduling paradigm, named PRedictable Execution Model (PREM); and 2) a framework of novel application-transparent, kernel-level techniques to perform fine-grained resource reservation of cache space and memory bandwidth in multi-core real-time systems.

We have successfully implemented and tested the proposed framework on a commodity ARM-based system and on a Freescale P4080 platform; it can also be applied to a variety of other platforms currently available on the market.  Finally, experimental benchmark results show that employing the proposed techniques to eliminate (last level) cache and memory bandwidth interference can lead up to a 250% improvement of the measured execution time.